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Synthesis and Static Time Analysis 6 Months

The graduates from Electronics/Electrical domain will be learning the basics of SoC in their academics. With the core knowledge of Design Verification, students can compete with ease for employability in semiconductor industries. Also, the working professionals who have a desire in pursuing their careers in ASIC design can opt for this course. The current demands of industries are analyzed, and the course content is set accordingly.

Module 1 : Synthesis

  • Introduction to Synthesis and its flow
  • Constraining Design for timing, area & power
  • Understanding & Exploring .lib
  • Synthesizing the Design
  • Checks on Timing
  • Reports, Analysis and Debugging of results
  • Optimization Techniques
  • Low Power Synthesis using UPF

Module 2 : Static Timing Analysis

  • Fundamentals of STA
  • Delays & Libraries
  • Constraining design using SDC commands
  • Clock generations, Handling Clocks and Cock exceptions
  • Timing Exceptions
  • Post Layout STA using SPEF
  • Multi-Mode, Multi-Corner STA
  • Cross talk & Noise Analysis
  • Timing ECOs generation, What-If Analysis
  • Timing Challenges

Module 3 : Analog Circuit Design

  • MOS fundamentals and characteristics
  • Current Mirror
  • Single-ended MOS amplifiers
  • Single-ended and differential signaling
  • CMOS Differential Amplifier
  • Stability Analysis
  • Operational Transconductance Amplifier
  • Two stage OPAMPS
  • Designing OPAMP using current source

Jordan Reynolds

Trainer

The Trainer has hands-on experience of about 21+ years in ASIC Design Verification. The trainer is passion-driven and has mentored several freshers and working professionals towards enhancing their skills & knowledge.

The Co-trainer has a command over the theory and LAB aspects of Design Verification.

Apart from the regular Trainers, a senior consultant from the industry will be visiting regularly to upgrade the skills & knowledge of the students.

Online Courses

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Classroom Courses

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