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Design Verification Engineering 6 Months

SoC Verification is a process in which a design is tested (or verified) against a given design specification before tape-out. This happens along with the development of the design and can start from the time the design architecture definition happens. The main goal of verification is to ensure the functional correctness of the design before the tape out. However, with increasing design complexities, the scope of verification is also evolving to include much more than functionality. This includes verification of performance and power targets, security and safety aspects of design and complexities with multiple asynchronous clock domains.

The graduates from Electronics/Electrical domain will be learning the basics of VLSI in their academics. With the core knowledge of Design Verification, students can compete with ease for employability in semiconductor industries. Also, the working professionals who have a desire in pursuing their careers in ASIC design can opt for this course. The current demands of industries are analyzed, and the course content is set accordingly.

Module 1 : Digital Fundamentalsting

  • MOS Concepts
  • Combinational Logic
  • Sequential Logic
  • Counters, Sequence Detectors, State Machines
  • Timing Aspects

Module 2 : Basics of Linux and Perl Introduction to Digital Design and Verification using System Verilog and Verilog

  • Data Types
  • Arrays
  • Procedural Statements & Control Flow
  • Placement, STA
  • Processes
  • Tasks & Functions
  • Classes
  • Randomization & Constraints
  • Inter Process Communication
  • Assertion
  • Coverage

Module 3 : Advanced Verification

Test Bench (TB) Development

  • Linear TB
  • File IO TB
  • State Machine based TB
  • Task based TB
  • Self-Checking TB
  • Bus Functional Model
  • Driver
  • Protocol Monitor
  • Score Board
  • Functional Coverage

Verification Flow

  • Planning Verification Environment Architecture
  • Feature Extraction from Specification

Direct Programming Interface (DPI)

Mini Project (Using Bus Interface)

Module 4 : Universal Verification Method

UVM Structure for a UVC

  • Introduction
  • UVM TB
  • UVM Sequence
  • UVM Configuration
  • UVM Phases
  • UVM Driver
  • UVM Monitor
  • UVM Scoreboard
  • UVM Environment
  • UVM Test
  • UVM TB top with example

UVM Structure for a UVC

  • UVM callback
  • UVM Events
  • UVM TLM
  • UVM Barrier
  • UVM Heartbeat

Mini Project

  • AHB UVC
  • Module 5 : Additional Advanced Topics

    • Gate Level Simulation
    • Power Simulation
    • Assertion Based Verification
    • H/W-S/W Co-simulation
    • Functional Safety (Fault Injection)
    • Formal Verification
    • Regression
    • AMS Modeling
    • Perspec System Verifier

    Jordan Reynolds

    Trainer

    The Trainer has a hands-on experience of about 21+ years in ASIC Design Verification. The trainer is passion driven and has mentored several freshers and working professionals towards enhancing their skills & knowledge.
    The Co-trainer has a command over the theory and LAB aspects of Design Verification.
    Apart from the regular Trainers, a senior consultant from the industry will be visiting regularly to upgrade the skills & knowledge of the students.

    Online Courses

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    Classroom Courses

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