Design for Test Engineering 6 Months

Design for Test (DFT) is one of the specializations in SOC flow. Testability is a design attribute that measures how easy it is to create a program to comprehensively test a manufactured design’s quality. Traditionally, design and test processes were kept separate, with test considered only at the end of the design cycle. But in contemporary design flows, test merges with design much earlier in the process, creating an important niche area called Design-for-Test (DFT) process flow.

The graduates from Electronics/Electrical domain will be learning the basics of VLSI in their academics. With the core knowledge of Design for test, students can compete with ease for employability at semiconductor industries. Also, the working professionals who have a desire in pursuing their career in ASIC design and test can opt for this course. The current demands of industries are analysed, and the course content are set accordingly.

Module 1 : Digital Fundamentals

  • MOS Concepts
  • Combinational Logic
  • Sequential Logic
  • Counters, Sequence Detectors, State Machines
  • Timing Aspects

Module 3 : DFT Fundamentals

Test Bench (TB) Development

  • Introduction to DFT
  • Need of DFT
  • DFT flow in SOC
  • DFT Architecture
  • DFT Methods
  • DFT Approach
  • OCC Architecture
  • Summary

Module 4 : Scan Insertion

  • Introduction
  • Scan Architecture
  • Inputs and outputs
  • DRC checks
  • Scan Insertion
  • Scan Types
  • Scan Styles
  • Lock up Latches Insertion
  • Summary

Module 5 : Compression

  • Introduction
  • Why compression
  • Compression Architecture
  • Compression ratio
  • Compression mode and bypass mode
  • Inputs and outputs
  • DRC
  • Masking logic
  • Summary

Module 6 : Scan Insertion

  • Introduction
  • ATPG Algorithm
  • Inputs and outputs
  • ATPG fault models
  • stuckat
    transition
    path delay
    bridging

  • DRC
  • Fault classes
  • Scan compression pattern generation.
  • Test coverage and fault coverage
  • Coverage analysis
  • Summary

Module 7 : Simulation

  • Introduction
  • Types of Simulation
  • Serial and parallel simulation
  • Difference between serial and parallel simulation Inputs and outputs
  • Inputs and outputs
  • Simulation Mismatches.
  • Summary

Module 8 : MBIST

  • Introduction
  • MBIST Architecture and flow
  • Inputs and outputs
  • Need of MBIST
  • Advantage and disadvantage of MBIST
  • MBIST Algorithms
  • Types of memory testing
  • Memory Fault types
  • Memory Repair
  • Summary

Module 9 : Simulation

  • Introduction
  • Types of Simulation
  • Serial and parallel simulation
  • Difference between serial and parallel simulation Inputs and outputs
  • Inputs and outputs
  • Simulation Mismatches.
  • Summary

Module 10 : MBIST

  • Introduction
  • MBIST Architecture and flow
  • Inputs and outputs
  • Need of MBIST
  • Advantage and disadvantage of MBIST
  • MBIST Algorithms
  • Types of memory testing
  • Memory Fault types
  • Memory Repair
  • Summary

Jordan Reynolds

Trainer

The Trainer has a hands-on experience of about 21+ years in ASIC Design Verification. The trainer is passion driven and has mentored several freshers and working professionals towards enhancing their skills & knowledge.
The Co-trainer has a command over the theory and LAB aspects of Design Verification.
Apart from the regular Trainers, a senior consultant from the industry will be visiting regularly to upgrade the skills & knowledge of the students.

Online Courses

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Classroom Courses

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